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8K X 8 BIT LOW POWER CMOS SRAM

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The AS6C6264A is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6- transistor cell. The circuit is activated by the rising edge of E2 (at E1 = L), or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0 - DQ7. After the address change, the data outputs go High-Z until the new read information is available. The data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the address, data input and control signals W or G, the operating current (at IO = 0 mA) drops to the value of the operating current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. This gate circuit allows to achieve low power standby requirements by activation with TTLlevels too.

8K X 8 BIT LOW POWER CMOS SRAM

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  • Density: 64K Low Power - EOL
  • Organistation: 8K X 8
  • VCC: 5V
  • See Datasheet for all other product variations and specifications
Data Sheet

 

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